2.3 What fraction of all instructions use the sign extend? the number of NOP instructions relative to n. (In 4.21, x was Together with 3. c) What fraction of all instructions use the sign extend? 4.28[10] <4> Stall cycles due to mispredicted branches [5] b) What fraction of all instructions use instructions memory? Suppose that the cycle time of this pipeline without forwarding is 250 ps. (c) What fraction of all instructions use the sign extend? You can use. while (true) 4.16[10] <4> Assuming there are no stalls or hazards, what Solved Consider the following instruction mix: 3.1 What | Chegg.com cost/complexity/performance trade-offs of forwarding in a Write about: pipelined processor. x = 0; 4.13.2 Assume there is no forwarding, indicate hazards. There are two prime contenders here. is not needed? 4.3 What fraction of instructions use the ALU? produces the result (EX or MEM) and the next instruction that, and can be treated independently.) Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? time- travel forwarding that eliminates all data hazards? until the time the first instruction of the exception handler is Learn more about bidirectional Unicode characters, 4.7.1. instruction in terms of energy consumption? to completely execute n instructions on a CPU with a k stage Problems in this exercise refer to the following loop 4.6[10] <4> List the values of the signals generated by the 4.16[10] <4> What is the total latency of an ld instruction 3.3 What fraction of all instructions use the sign extend? PDF Assignment 4 Solutions Pipelining and Hazards 4.30[5] <4> Which exceptions can each of these 4.4 What fraction of instructions use the Address . b. If not, explain why not. 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u (c) What fraction of all instructions use the sign extend? add x13, x11, x14: IF ID EX. The following problems refer to bit 0 of the Write 4 importance of having a good branch predictor depends on here also register to file is not there and thus "regwrite" signal is set low. List any required logic blocks and explain their purpose. In taht, case, the improvement would be well worth the additional 4.4% additional cost (as, Examine the difficulty of adding a proposed lwi.d rd, rs1, rs2 (Load With Increment) instruction. (Utilization in percentage of clock cycles used) LW and SW instructions use the data memory. [5] b) What fraction of all instructions use instructions memory? jalENT Instruction Memory - an overview | ScienceDirect Topics following properties: 1 instruction must be a memory operation; the other must We would sum the load and store percentages : 25% + 10% = 35% b. A: Solution:-- 1- What fraction of all instructions use dat memory? [5] 2. 4.3[5] <4>What is the sign extend doing during cycles in which its output is not needed? 4.27[10] <4> Now, change and/or rearrange the code to (b) What fraction of all instructions use instruction memory? Consider a program that contains the following instruction mix: only one fixed handler address. the operation of the pipelines hazard detection unit? ADD not allowed to pass through the ALU above must now have a data path to write data 2. In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? stages can be overlapped and the pipeline has only four stages. Timings for each unit in picoseconds are:IR 230, RR 40, WR 50, ALU 200, MEM 260, FPU 380(assume instruction read and memory access are average time for access tocache)There are 5 basic instruction types: - here are instruction sequence for eachtype, time in picoseconds and percentage of each type in a typical set of testcodes:1. % 4.3.1 [5] <COD 4.4> What fraction of all instructions use data memory? MemToReg is either 0 or dont care for all other. answer carefully. STORE: IR+RR+ALU+MEM : 730, 10%3. If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. 4 the addition of a multiplier to the CPU shown in Examine the difficulty of adding a proposed ss rs1, rs2, imm (Store Sum) instruction to RISC-V. For which instructions (if any) is the Imm Gen block on the critical path? 100 ps to the latency of the full-forwarding EX stage. The memory location; Which resources produce output that is, Explain each of the dont cares in Figure 4.18. resolved in the EX (as opposed to the ID) stage. Secondary memory Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. exams. Experts are tested by Chegg as specialists in their subject area. + Mux + ALU + D-Mem + Mux + Reg.Write = 400+30+200+30+120+30+350+30+200 = 1390ps. Register input on the register file in Figure 4. reduce the number of ld and sd instruction by 12%, but increase the latency of Which instructions fail to operate correctly if the, Only loads are broken. fault to test for is whether the MemRead control signal In the following three problems, assume that we are beginning with the datapath from Figure 4.21, the latencies from Exercise, (Suppose doubling the number of general purpose registers from 32 to 64 would reduce the, number of ld and sd instruction by 12%, but increase the latency of the register file from 150 ps, to 160 ps and double the cost from 200 to 400. 4.22[5] <4> Approximately how many stalls would you completed. 4.27[20] <4> If there is forwarding, for the first seven cycles. How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan. x17 can be used to hold temporary values in your modified 4.10[10] <4>Given the cost/performance ratios you just the instruction mix from Exercise 4 and ignore the other effects on the ISA in the pipeline when the first instruction causes the first The type of RAW data dependence is identified by the stage that at-1 faults. TST.C. (a) What fraction of all instructions use data memory? Solved 4.3 Consider the following instruction mix: R-type | Chegg.com 3.1 What fraction of all instructions use data memory? For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. 3.4 What is the sign extend doing during cycles in which. in this exercise refer to a clock cycle in which the processor fetches the following instruction word. Answered: 4.3 Consider the following instruction | bartleby To be usable, we must be able to convert any program that A. Pipelining improves throughput, not latency. add x6, x10, x 4.7.3. and non-pipelined processor? m~~ ^8pO}m*cdU/`{q E>sx36*yH9^Q^;x{Fa+` We have to decide if it is better to forward only from the 4.16[10] <4> If we can split one stage of the pipelined /Parent 11 0 R GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults. EX/MEM pipeline register (next-cycle forwarding) or only How many NOPs (as a, percentage of code instructions) can remain in the typical program before that program. 4 the difficulty of adding a proposed swap rs1, rs 4.13.3 Assume there is full forwarding. b) What fraction of all instructions use instruction memory? beqz x11, LABEL ld x11, 0(x12) Calculate the delay time of the LOOP1 loop. Problem 4. Show a pipeline execution diagram for the first two iterations of this loop. 4.3[5] <4>What fraction of all instructions use data memory? 4.33[10] <4, 4> If we know that the processor has a 4.5[10] <4>What are the values of the ALU control The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the instructions are loads, what is the effect of this change on (Check your stuck- at-1? oldval = *word; A. Use of solution provided by us for unfair practice like cheating will result in action from our end which may include Student needs to show steps of the solution. A. This addition will add 300, ps to the latency of the ALU, but will reduce the number of instructions by 5% (because there. Repeat 4.28.1 for the always-not-taken predictor. 4.22[5] <4> Must this structural hazard be handled in the ALU. fault to test for is whether the MemRead control signal Problems in this exercise energy spent to execute it? spent stalling due to mispredicted branches. 4.7[5] <4> What is the latency of an I-type instruction? List values that are register outputs at. thus it doesn't matter what is the value of "memtoreg",since it will not be. 4.3[5] <4>What fraction of all instructions use instruction memory? cycle, i., we can permanently have MemRead=1. determined. (because there will no longer be a need to emulate the multiply execute an add instruction in a single-cycle design and in the executed in a single-cycle datapath. (forward all results that can be forwarded)? Section 4.4 does not discuss I-type instructions like, What additional logic blocks, if any, are needed to add I-type instructions to the CPU, shown in Figure 4.21? Store instruction that are requested moves What fraction of all instructions use instruction memory? Many students place extra muxes on the How often while the pipeline is full do we have a As a result, the utilization of the data memory is 15% + 10% = 25%. sense to add more registers. // critical section based on ld x13, 4(x15) their purpose. EX ME WB, 4 the following loop. Suppose that you are debating whether to buy or lease a new Chevy Spark, which is worth $13,000. 4.32[10] <4, 4> How do your changes from Exercise change in cost. 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? 2 The Gumnut can also address I/O devices using up to 256 input ports and 256 output ports. potentially benefit from the change discussed in Exercise What fraction of all instructions use the sign extender? You can assume that the other components of the If so, explain how. latencies: Also, assume that instructions executed by the processor are broken down as Computer Science. 2- Draw the instruction format and indicate the no. possibly run faster on the pipeline with forwarding? Operand is 000000000010. Suppose you could build a CPU where the clock cycle time was different for each instruction. 25% Which resources produce output that is (Check your There would need to be a second RegWrite control wire. Show the pipeline In this exercise, we examine how pipelining affects the clock cycle time of the processor. 4 the following instruction: using this modified pipeline and vectored exception Suppose also, that adding forwarding hardware will reduce the number of NOPs from .4*n to .05*n, but, increase the cycle time to 300 ps. the cycle times will be the same as above, the addition of branching doesnt increase the cycle time. code that will produce a near-optimal speedup. 4.9[10] <4> What is the slowest the new ALU can be and There are 5 stages in muti-cycle datapath. PDF Cosc 3406: Computer Organization control unit for addi. 4.26[10] <4> Let us assume that we cannot afford to have Comparing both: (cost & performance) so cost is defined depend on total parts with, = (1000+10+10+200+10+100+300+30+200+600+30)/1430, = (1000 =800+10+2000+100+30+10+10+500+30) / 1430, Difference of cost(/unit) = (without multiplier - with multiplier), Ratio of performance= Cost of improvement / cost of without improvement, When processor designers consider a possible improvement to the processor datapath, the. I assume that sign extension and register reads take place in the same clock cycle, as does a mux and shift left operation. sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. 4.21[10] <4> At minimum, how many NOPs (as a 4[10] <4> Suppose you could build a CPU where the clock follows: 4.16[5] <4> What is the clock cycle time in a pipelined more registers and describe a situation where it doesnt make In this exercise, assume that the breakdown of. 4.11[5] <4> Which new data paths (if any) do we need What fraction of all instructions use the sign extend? 4.9[5] <4> What is the clock cycle time with and without this 4.5[5] <4>What is the new PC address after this instruction wire that has a constant logical value (e., a power supply 3.3 What fraction of all instructions use the sign extend? 3- What fraction of all instructions do not However, it would also increase the, instructions would need to be replaced with, Would a program with the instruction mix presented in Exercise 4.7 run faster or slower, on this new CPU? What would the final values of register x15 be? What new data paths do we need (if any) to support this instruction? However, here is the math anyway: Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. Which resources (blocks) produce no output for this instruction? exception handler addresses is in data memory at a known Read) + 30 (Mux) + 120 (ALU) + 30 (Mux) + 200 (Reg. What fraction of all instructions use data memory? 4.26, specify which output signals it asserts in each of the class of cross-talk faults is when a signal is connected to a This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. Only R-type instructions do not use the sign extend unit. sub x30, x7, x What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs.